Array-of-arrays architecture for parallel floating point multiplication

This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the IEEE standard 754 for floating point multiplication, and tested for functionality in Verilog. The design, which was done in dual-rail domino, was simulated in HSpice with estimated capacitive load models in a 1µm CMOS technology. Multiplication latency of 10ns (23.3 FO4) at 4.3V supply and 1200C can be achieved with the best topology of the array-of-arrays architecture. The estimated multiplier area is 3mm x 6mm.

• Type: Conference
• Year: 1995
• Where: ARVLSI
• Authors: H. Dhanesha, K. Falakshahi, Mark Horowitz
• Keywords: 53-bit Mantissa Path, ARVLSI 1995, Capacitive Load Models, VLSI, floating Point Multiplier