ASIP architecture for multi-standard wireless terminals

This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireless terminals. Thanks to a high level of parallelism and a consistent use of pipeline, the BPE architecture fully satisfies stringent real-time constraints imposed by emerging technologies. Its efficiency has been proven through the implementation, the physical synthesis for the CMOS 90nm STM technology and the FPGA prototyping on the ARM Versatile platform of a dualstandard Frequency Domain Equalizer (FDE) supporting the 3GPP HSDPA and the IEEE 802.11a standards.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Daniele Lo Iacono, J. Zory, Ettore Messina, N. Piazzese, G. Saia, A. Bettinelli
• Keywords: DATE 2006, Hardware, Multistandard Wireless Terminals, Specific Instruction-Set Processor, Stringent Real-time Constraints