Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs

Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing power consumption in NoCs is a critical challenge. One approach to reduce power is to dynamically scale the voltage and frequency of each network node or groups of nodes (DVFS). Another approach to reduce power consumption is to replace the balanced clock tree with a globally-asynchronous, locally-synchronous (GALS) clocking scheme. NoCs implemented with either of these schemes, however, tend to have high latencies as packets must be synchronized at intermediate nodes between source and destination. In this paper, we propose a novel router microarchitecture which offers superior performance versus typical synchronizing router designs. Our approach features Asynchronous Bypass Channels (ABCs) at intermediate nodes thus avoiding synchronization delay. We also propose a new network topology and routing algorithm t...

• Type: Journal
• Year: 2010
• Where: NOCS
• Authors: Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi
• Keywords: Computer Networks, Design, Intermediate Nodes, NOCS 2010, Power Consumption