An Asynchronous Interconnect Architecture for Device Security Enhancement

We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the most prominent being security enhancements, a reduction in the number of wires required, no need for clock distribution or packetization, and ease of composition. We give some sample throughput and latency figures from simulation on a 0.18?m technology and show that it is viable for use with modern interconnect requirements, is of low complexity and has a lower area requirement than parallel interconnect over distances as short as 1mm.

• Type: Conference
• Year: 2006
• Where: VLSID
• Authors: Simon Hollis, Simon W. Moore
• Keywords: Asynchronous Gasp Architecture, Computer Architecture, Modern Interconnect Requirements, On-chip Interconnect, VLSID 2006