Automatic Constraint Based Test Generation for Behavioral HDL Models

The proposed work involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. The method is demonstrated for the 16-bit DLX-architecture.

• Type: Journal
• Year: 2008
• Where: TVLSI
• Authors: Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil
• Keywords: Circuit Model, TVLSI 2008