Global Multi-Threaded Instruction Scheduling

Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro-architectural limitations. Despite this move, CMPs do not directly improve the performance of singlethreaded codes, a characteristic of most applications. In order to support parallelization of general-purpose applications, computer architects have proposed CMPs with lightweight scalar communication mechanisms [21, 23, 29]. Despite such support, most existing compiler multi-threading techniques have generally demonstrated little effectiveness in extracting parallelism from non-scientific applications [14, 15, 22]. The main reason for this is that such techniques are mostly restricted to extracting parallelism within straight-line regions of code. In this paper, we first propose a framework that enables global multi-threaded instruction scheduling in general. We then describe GREMIO, a scheduler built using...

• Type: Conference
• Year: 2007
• Where: MICRO
• Authors: Guilherme Ottoni, David I. August
• Keywords: Compiler Multi-threading Techniques, Hardware, MICRO 2007, Multi-threading Technique, Non-speculative Thread-level Parallelism