BETSY: synthesizing circuits for a specified BIST environment

This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specified BIST environment. Instead of optimizing the circuitfor a generic pseudo-random test pattern generator (by maximizing its random pattern testability), the circuit is optimized for a specific test pattem generator, e.g., an LFSR with a specific characteristic polynomial and initial seed. This solves the problem of having to estimate fault detection probabilities during synthesis and guarantees that the resulting circuit achieves 100% fault coverage. BETSY considers the exact set of patterns that will be applied to the circuit during BIST and applies various transfomations to generate an implementation that isfully tested by those patterns. When needed, BETSY inserts test points early in the synthesis process in an optimal way and accountsfor them in satisfying timing constraints and other synthesis criteria...

• Type: Conference
• Year: 1998
• Where: ITC
• Authors: Zhe Zhao, Bahram Pouya, Nur A. Touba
• Keywords: Bist Environment, Environment Testable Synthesis, Hardware, ITC 1998, Test Pattern Generator