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ITC
1998
IEEE
126views Hardware» more  ITC 1998»
14 years 3 months ago
A comprehensive approach to the partial scan problem using implicit state enumeration
This paper presents a novel technique to evaluate the noncontrollability measures of state registers for partial scan design. Our model uses implicit techniques for finite state ma...
Priyank Kalla, Maciej J. Ciesielski
ITC
1998
IEEE
66views Hardware» more  ITC 1998»
14 years 3 months ago
A novel combinational testability analysis by considering signal correlation
Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chi...
ITC
1998
IEEE
94views Hardware» more  ITC 1998»
14 years 3 months ago
Testing embedded-core based system chips
Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design, in which every circuit is designed from scratch and reuse...
Yervant Zorian, Erik Jan Marinissen, Sujit Dey
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
14 years 3 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
ITC
1998
IEEE
94views Hardware» more  ITC 1998»
14 years 3 months ago
A method of serial data jitter analysis using one-shot time interval measurements
A method for measuring inter-symbol interference, duty cycle distortion, random jitter and periodic jitter is described. The Blackman-Tukey method of signal analysis is used. This...
Jan B. Wilstrup
ITC
1998
IEEE
59views Hardware» more  ITC 1998»
14 years 3 months ago
Stimulus generation for built-in self-test of charge-pump phase-locked loops
Abstract - This paper addresses the issue of the stimulation of charge-pump phase-locked loops for built-in selftest applications. It is shown that three nodes of the PLL qualify f...
Benoît R. Veillette, Gordon W. Roberts
ITC
1998
IEEE
86views Hardware» more  ITC 1998»
14 years 3 months ago
An introduction to area array probing
Frederick L. Taber
ITC
1998
IEEE
104views Hardware» more  ITC 1998»
14 years 3 months ago
Built-in self-test of FPGA interconnect
: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affect...
Charles E. Stroud, Sajitha Wijesuriya, Carter Hami...
ITC
1998
IEEE
95views Hardware» more  ITC 1998»
14 years 3 months ago
Native mode functional test generation for processors with applications to self test and design validation
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
Jian Shen, Jacob A. Abraham