Optimal latch mapping and retiming within a tree

We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined circuits. If the circuit to be mapped has a tree structure, our algorithm generates an optimal solution compatible with that structure. The algorithm takes into account gate delays and capacitive loads as latches are moved across the logic. It also supports latches with embedded logic: i.e., cells that combine a D latch with a combinational gate at little extra cost in latch delay. simple transparent latch and a gate (denoted f(x1,x2,...,xn)) for only little more delay and area than the latch itself. These cell libraries are often incomplete; e.g., a typical cell library based on tristate latches may embed only D, AND2, AND3, and OR2 gates in latches, disallowing larger gates and inverting gates. For such asymmetric libraries, a simple change of latch polarity (i.e., retiming across an inverter) may enable or di...

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann
• Keywords: Gate, Hardware, ICCAD 1994, Latch, Simple Transparent Latch