BIST for Deep Submicron ASIC Memories with High Performance Application

Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on memories that now operate in the 10 to 800 MHz range can be a challenge. Another demand upon memory BIST is determining the location of defects so that the cause can be diagnosed, or repaired with redundant cells. A tool and methodology that meets these difficult requirements is discussed.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai
• Keywords: At-speed Testing, Hardware, ITC 2003, Memory Bist, Memory Bist Requirements