A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs

Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful functional decomposition algorithm. The impact of decomposition is enhanced by a preceding collapsing step. To decompose functions for small depth and area, we present an iterative, BDD-based variable partitioning procedure. The procedure optimizes the variable partition for each bound set size by iteratively exchanging variables between bound set and free set, and finally selects a good bound set size. Our decomposition algorithm extracts common subfunctions of multiple-output functions, and thus further reduces area and the maximum interconnect lengths. Experimental results show that our new algorithm produces circuits with significantly smaller depths than other performance-oriented mappers. This advantage also holds for the actual delays after placement and routing.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Christian Legl, Bernd Wurth, Klaus Eckl
• Keywords: Bound Set, Bound Set Size, Computer Architecture, DAC 1996, Decomposition Algorithm