C-Pack: A High-Performance Microprocessor Cache Compression Algorithm

Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memory. Accessing off-chip memory generally takes an order of magnitude more time than accessing on-chip cache, and two orders of magnitude more time than executing an instruction. Computer systems and microarchitecture researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. However, most past work, and all work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the proposed compression algorithms and hardware. It is not possible to determine whether compression at levels of the memory hierarchy closest to the processor is beneficial without understanding its costs. Furthermore, as we show in this paper, raw compressi...

• Type: Journal
• Year: 2010
• Where: TVLSI
• Authors: Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris Lekatsas
• Keywords: Artificial Intelligence, Cache, Compression Algorithm, On-chip Cache, TVLSI 2010