Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach

The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application and limitations of the architecture. In a topdown approach a real-time MPEG 1 Layer 3 (MP3) decoder is designed on this SoC, which integrates FPGA resources and an AVR microcontroller core within a single chip. An intensive design space exploration based on simon different levels of abstractions is fundamental for a real-time implementation on this limited architecture. After determining a suited functional partitioning a special DSP is implemented on the FPGA, wherefore an instruction set simulator is build, which allows concurrent HW/SW development.

• Type: Conference
• Year: 2004
• Where: VLSID
• Authors: Jens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger
• Keywords: AVR Microcontroller Core, Computer Architecture, Instruction Set Simulator, Intensive Design Space, VLSID 2004