Cache vulnerability equations for protecting data in embedded processor caches from soft errors

Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, caches are most vulnerable to soft errors, and techniques at various levels of detraction, e.g., fabrication, gate design, circuit design, and microarchitecture-level, have been developed to protect data in caches. However, no work has been done to investigate the effect of code transformations on the vulnerability of data in caches. Data is vulnerable to soft errors in the cache only if it will be read by the processor, and not if it will be overwritten. Since code transformations can change the read-write pattern of program variables, they significantly effect the soft error vulnerability of program variables in the cache. We observe that often opportunity exists to significantly reduce the soft error vulnerability of cache data by trading-off a little performance. However, even if one wanted to exploit this...

• Type: Conference
• Year: 2010
• Where: LCTRTS
• Authors: Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul
• Keywords: LCTRTS 2010, Soft Error Vulnerability, Soft Errors, Vulnerability