Capacitor mismatch error cancellation technique for a successive approximation A/D converter

An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in the conversion time, the firstorder capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated opamp is explained. SWITCAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under non-ideal conditions, including 1% 3 nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB opamp gain, and 30 mV opamp offset.

• Type: Conference
• Year: 1999
• Where: ISCAS
• Authors: Zhiliang Zheng, Un-Ku Moon, Jesper Steensgaard, Bo Wang, Gabor C. Temes
• Keywords: Capacitor Mismatch, Capacitor Mismatch Error, Hardware, ISCAS 1999, Nominal Capacitor Mismatch