A case for heterogeneous on-chip interconnects for CMPs

Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the entire network. While this homogeneous network design eases the burden on a network designer, partitioning the resources equally among all routers across the network does not lead to optimal resource usage, and hence, affects the performance-power envelope. In this work, we propose to apportion the resources in an NoC to leverage the non-uniformity in network resource demand. Our proposal includes partitioning the network resources, specifically buffers and links, in an optimal manner. This approach results in redistributing resources such that routers that require more resources are allocated more buffers and wider links compared to routers demanding fewer resources. This results in a novel heterogeneous network, called HeteroNoC, which is composed of two types of routers – small power efficient routers, and...

• Type: Journal
• Year: 2011
• Where: ISCA
• Authors: Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
• Keywords: Hardware, Homogeneous Network, ISCA 2011, Memory Controllers, Performance Routers