Checkpointed Early Load Retirement

Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions, they also prevent other instructions from moving through the in-order reorder buffer (ROB) and retire. As a result, the processor quickly fills up with uncommitted instructions, and computation ultimately stalls. To attack this problem, we propose checkpointed early load retirement, a mechanism that combines register checkpointing and back-end--i.e., at retirement--load-value prediction. When a long-latency load hits the ROB head unresolved, the processor enters Clear mode by (1) taking a Checkpoint of the architectural registers, (2) supplying a Load-value prediction to consumers, and (3) EARly-retiring the long-latency load. This unclogs the ROB, thereby "clearing the way" for subsequent instructions to retire, and also allowing instructions dependent on the long-latency load to execute sooner. W...

• Type: Conference
• Year: 2005
• Where: HPCA
• Authors: Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
• Keywords: Computer Architecture, Dependent Instructions, Early Load Retirement, HPCA 2005, Subsequent Instructions