Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three designs randomly injected with 5 node-type or stuck-at faults.

• Type: Conference
• Year: 2003
• Where: ATS
• Authors: Yu-Chiun Lin, Shi-Yu Huang
• Keywords: ATS 2003, Fault Diagnosis, Hardware, Multiple Faults, Structural Dependent Faults