Sciweavers

ET
2006
98views more  ET 2006»
13 years 10 months ago
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
1 Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of the...
Yu-Chiun Lin, Shi-Yu Huang
AMCS
2008
146views Mathematics» more  AMCS 2008»
13 years 10 months ago
Fault Detection and Isolation with Robust Principal Component Analysis
Principal component analysis (PCA) is a powerful fault detection and isolation method. However, the classical PCA which is based on the estimation of the sample mean and covariance...
Yvon Tharrault, Gilles Mourot, José Ragot, ...
WM
2003
14 years 2 days ago
Evaluation of two Strategies for Case-Based Diagnosis handling Multiple Faults
: Case-based diagnosis handling multiple faults is still a challenging task. In this paper we present methods for handling multiple faults, embedded in the standard CBR cycle. The ...
Martin Atzmüller, Joachim Baumeister, Frank P...
ATS
1998
IEEE
113views Hardware» more  ATS 1998»
14 years 3 months ago
Testing and Diagnosis of Interconnect Structures in FPGAs
Since Field programmable gate arrays (FPGAs) are reprogrammable, faults in them can be easily toleruted once fault sites are located. Previous researches on diagnosis of FPGAs mai...
Sying-Jyan Wang, Chao-Neng Huang
ITC
2003
IEEE
153views Hardware» more  ITC 2003»
14 years 4 months ago
An Efficient and Effective Methodology on the Multiple Fault Diagnosis
In this paper, we analyze failing circuits and propose a multiple-fault diagnosis approach. Our methodology has been validated experimentally and has proved to be highly efficient...
Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadow...
ATS
2003
IEEE
110views Hardware» more  ATS 2003»
14 years 4 months ago
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...
Yu-Chiun Lin, Shi-Yu Huang
ETFA
2006
IEEE
14 years 4 months ago
Robust Fault Isolation Filter Design for Networked Control Systems
In this paper, the effect of network-induced delay introduced into the control loop is modelled as time-varying disturbance. Based on this model, a fault isolation filter (FIF) f...
Shanbin Li, Dominique Sauter, Christophe Aubrun
DSD
2007
IEEE
105views Hardware» more  DSD 2007»
14 years 5 months ago
Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment
With continuing increase in soft error rates, its foreseeable that multiple faults will eventually need to be considered when modeling circuit sensitivity and evaluating faulttole...
Christian J. Hescott, Drew C. Ness, David J. Lilja
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 5 months ago
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints
In this paper we present an approach to the synthesis of fault-tolerant schedules for embedded applications with soft and hard real-time constraints. We are interested to guarante...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...
IOLTS
2009
IEEE
174views Hardware» more  IOLTS 2009»
14 years 5 months ago
ATPG-based grading of strong fault-secureness
—Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considere...
Marc Hunger, Sybille Hellebrand, Alejandro Czutro,...