A chip-level electrostatic discharge simulation strategy

This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node VDD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.

• Type: Conference
• Year: 2004
• Where: ICCAD
• Authors: Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar
• Keywords: DC Analysis Problem, Hardware, ICCAD 2004, Incremental Changes, Network Reduction Algorithm