On-chip networks: A scalable, communication-centric embedded system design paradigm

As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts. More and more processor cores and large, reusable components are being integrated on a single silicon die but reuse of the communication infrastructure has been difficult. Buses and point to point connections, that have been the main means to connect components on a chip today, will not result in a scalable platform architecture for the billion transistor chip era. Buses can cost efficiently connect a few tens of components. Point to point connections between communication partners is practical for even fewer components. As more and more components are integrated on a single silicon die, performance bottlenecks of long, global wires preclude reuse of buses. Therefore, scalable on-chip communication infrastructure is playing an increasingly dominant role in system-onchip designs. With the super-abundance of ...

• Type: Conference
• Year: 2004
• Where: VLSID
• Authors: Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
• Keywords: Computer Architecture, Efficient On-chip Communication, On-chip Communication Infrastructure, Scalable On-chip Communication, VLSID 2004