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VLSID
2004
IEEE
128views VLSI» more  VLSID 2004»
14 years 11 months ago
A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique
This work presents a novel dynamic bias control technique to verify the circuit performance of the lowpower rail-to-rail input/output buffer amplifier, which can be operating in s...
Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi
VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
14 years 11 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
VLSID
2004
IEEE
126views VLSI» more  VLSID 2004»
14 years 11 months ago
Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes
In order to break the 100 W average power barrier of a wireless microsensor node, aggressive design methodologies need to be developed. Dynamic voltage scaling should be more aggr...
David D. Wentzloff, Benton H. Calhoun, Rex Min, Al...
VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
14 years 11 months ago
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization
It has been observed that even highly optimized software programs perform "redundant" computations during their execution, due to the nature (statistics) of the values a...
Weidong Wang, Anand Raghunathan, Niraj K. Jha
VLSID
2004
IEEE
120views VLSI» more  VLSID 2004»
14 years 11 months ago
Dynamic Power Optimization of Interactive Systems
Abstract-- Power has become a major concern for mobile computing systems such as laptops and handhelds, on which a significant fraction of software usage is interactive instead of ...
Lin Zhong, Niraj K. Jha
VLSID
2004
IEEE
95views VLSI» more  VLSID 2004»
14 years 11 months ago
Embedded Hardware Face Detection
Theo Theocharides, Greg M. Link, Narayanan Vijaykr...
VLSID
2004
IEEE
91views VLSI» more  VLSID 2004»
14 years 11 months ago
Program Slicing for ATPG-Based Property Checking
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
Vivekananda M. Vedula, Whitney J. Townsend, Jacob ...
VLSID
2004
IEEE
111views VLSI» more  VLSID 2004»
14 years 11 months ago
Improved Approach for Noise Propagation to Identify Functional Noise Violations
This paper targets at reducing the crosstalk noise closure time by filtering the set of false violations. We propose two approaches to reduce the pessimism in the crosstalk noise ...
Sachin Shrivastava, Dhanoop Varghese, Vikas Narang...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 11 months ago
High-Performance Power Grids For Nanometer Technologies
With shrinking noise margins and increasing numbers of on-chip noise sources, power grid design has become a critical performance determinant. This paper presents an overview of r...
Sachin S. Sapatnekar