Comparison of memory write policies for NoC based Multicore Cache Coherent Systems

The following study shows a direct comparison of memory write policies in Shared Memory Multicore Systems. Although there are much work and many studies about this issue, our work takes into account the difficulties related to on chip communication using network-like interconnects. Our study is based on Cycle Approximate Bit Accurate simulations (CABA) of platforms with up to 64 processors, modelling accurately all the aspects of multi-threaded program execution and memory accesses. Our main results show that write-through caches perform well compared to write-back ones, with a slightly simpler implementation and comparable traffic.

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: Pierre Guironnet de Massas, Frédéric Pétrot
• Keywords: Cycle Approximate Bit, DATE 2008, Hardware, Memory Write Policies, Shared Memory Multicore