A comprehensive approach to DRAM power management

This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe a simple power-down policy for exploiting low power modes of modern DRAMs; (2) we show how the idea of adaptive history-based memory schedulers can be naturally extended to manage power and energy; and (3) for situations in which additional DRAM power reduction is needed, we present a throttling approach that arbitrarily reduces DRAM activity by delaying the issuance of memory commands. Using detailed microarchitectural simulators of the IBM Power5+ and a DDR2-533 SDRAM, we show that our first two techniques combine to increase

• Type: Conference
• Year: 2008
• Where: HPCA
• Authors: Ibrahim Hur, Calvin Lin
• Keywords: Computer Architecture, DRAM Energy Efficiency, DRAM Power Reduction, HPCA 2008, Manage Dram Power