Sciweavers

HPCA
2008
IEEE
14 years 5 months ago
Prediction of CPU idle-busy activity pattern
Real-world workloads rarely saturate multi-core processor. CPU C-states can be used to reduce power consumption during processor idle time. The key unsolved problem is: when and h...
Qian Diao, Justin J. Song
HPCA
2008
IEEE
14 years 5 months ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
HPCA
2008
IEEE
14 years 11 months ago
Runahead Threads to improve SMT performance
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
Tanausú Ramírez, Alex Pajuelo, Olive...
HPCA
2008
IEEE
14 years 11 months ago
Fundamental performance constraints in horizontal fusion of in-order cores
A conceptually appealing approach to supporting a broad range of workloads is a system comprising many small cores that can be fused, on demand, into larger cores. We demonstrate ...
Pierre Salverda, Craig B. Zilles
HPCA
2008
IEEE
14 years 11 months ago
PaCo: Probability-based path confidence prediction
A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applica...
Kshitiz Malik, Mayank Agarwal, Vikram Dhar, Matthe...
HPCA
2008
IEEE
14 years 11 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
HPCA
2008
IEEE
14 years 11 months ago
Branch-mispredict level parallelism (BLP) for control independence
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control independence (CI) architectures look for useful con...
Kshitiz Malik, Mayank Agarwal, Sam S. Stone, Kevin...
HPCA
2008
IEEE
14 years 11 months ago
CMP network-on-chip overlaid with multi-band RF-interconnect
In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on...
M. Frank Chang, Jason Cong, Adam Kaplan, Mishali N...