Controlling Peak Power During Scan Testing

This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverage. The proposed approach works for any conventional full-scan design -- no extra design-for-test (DFT) logic is required. If the peak power in a clock cycle during scan testing exceeds a specified limit (which depends on the amount of peak power that can be safely handled without causing a failure that would not occur during normal functional operation) then a "peak power violation” occurs. Given a set of scan vectors, simulation is done to identify and classify the scan vectors that are causing peak power violations during scan testing. The problem scan vectors are then modified in a way that eliminates the peak power violations while preserving the fault coverage. Experimental results indicate the proposed procedure is very effective in controlling peak power.

• Type: Conference
• Year: 2002
• Where: VTS
• Authors: Ranganathan Sankaralingam, Nur A. Touba
• Keywords: Peak Power, Peak Power Violations, Scan Vectors, VLSI, VTS 2002