Recently proposed techniques for peak power management [18] involve centralized decisionmaking and assume quick evaluation of the various power management states. These techniques...
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, ...
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within ...
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as wel...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...