Cortical architectures on a GPGPU

As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for future computing devices, future chips will also likely suffer from more faulty devices and increased power consumption. It is also likely that these chips will be difficult to program if the current trend of adding more parallel cores continues to follow in the future. However, recent advances in neuroscientific understanding make parallel computing devices modeled after the human neocortex a plausible, attractive, fault-tolerant, and energy-efficient possibility. In this paper we describe a GPGPU extension to an intelligent model based on the mammalian neocortex. The GPGPU is a readily-available architecture that fits well with the parallel cortical architecture inspired by the basic building blocks of the human brain. Using NVIDIA’s CUDA framework, we have achieved up to 273x speedup over our unoptimized ...

• Type: Conference
• Year: 2010
• Where: ASPLOS
• Authors: Andrew Nere, Mikko Lipasti
• Keywords: ASPLOS 2010, Computing Devices, Cortical Architecture, Future Computing Devices, Programming Languages