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DATE
2004
IEEE

Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor

14 years 2 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current functional verification approaches. The paper reports on a large-scale experiment employing the CVE property checker for verifying the block-level functional correctness of a large ASIC. This new verification methodology achieves substantial quality and productivity gains. The two biggest advantages are:
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DATE
Authors Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
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