A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations

Abstract—A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In particular, 7nm FinFET devices are designed and simulated by using Synopsys TCAD tool suite, Sentaurus. Next, 6T and 8T SRAM cells, which are composed of these devices, are designed and optimized. To enhance the cell stability and reduce leakage energy consumption, the dual (i.e., front and back) gate control feature of FinFETs is exploited. This is, however, done without requiring any external signal to drive the back gates of the FinFET devices. Subsequently, the effect of process variations on the aforesaid SRAMs is investigated and steps are presented to protect the cells against these variations. More precisely, the SRAM cells are first designed to minimize the expected energy consumption (per clock cycle) subject to the non-destructive read and successful write requirements under worst-case process co...

• Type: Journal
• Year: 2015
• Where: ASPDAC
• Authors: Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram
• Keywords: ASPDAC 2015, Hardware