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ASPDAC
2015
ACM
21views Hardware» more  ASPDAC 2015»
8 years 7 months ago
BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies
Abstract—Modern high-speed links and I/O subsystems often employ sophisticated coding strategies to boost error resilience and achieve multiGb/s throughput. The end-to-end analys...
Aadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhu...
ASPDAC
2015
ACM
27views Hardware» more  ASPDAC 2015»
8 years 7 months ago
Modeling and optimization of low power resonant clock mesh
—Power consumption is becoming more critical in modern integrated circuit (IC) designs and clock network is one of the major contributors for on-chip power. Resonant clock has be...
Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang
ASPDAC
2015
ACM
17views Hardware» more  ASPDAC 2015»
8 years 7 months ago
An HDL-synthesized gated-edge-injection PLL with a current output DAC
– This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for ...
Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot...
ASPDAC
2015
ACM
19views Hardware» more  ASPDAC 2015»
8 years 7 months ago
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations
Abstract—A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In...
Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud...
ASPDAC
2015
ACM
19views Hardware» more  ASPDAC 2015»
8 years 7 months ago
A negative-resistance sense amplifier for low-voltage operating STT-MRAM
- This paper exhibits a 65-NM 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at 0.38V. The proposed sense amplifier comprises a boosted-gate ...
Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shi...
ASPDAC
2015
ACM
27views Hardware» more  ASPDAC 2015»
8 years 7 months ago
Automated generation of hybrid system models for reachability analysis of nonlinear analog circuits
Abstract— We address the problem of formally verifying nonlinear analog circuits with an uncertain initial set by computing their reachable set. A reachable set contains the unio...
Hyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoell...
ASPDAC
2015
ACM
23views Hardware» more  ASPDAC 2015»
8 years 7 months ago
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data
Passive macromodeling for RF circuit blocks is a critical task to facilitate efficient system-level simulation for large-scale RF systems (e.g., wireless transceivers). In this pa...
Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li 000...
ASPDAC
2015
ACM
16views Hardware» more  ASPDAC 2015»
8 years 7 months ago
Electromigration-aware redundant via insertion
As the feature size shrinks, electromigration (EM) becomes a more critical reliability issue in IC design. EM around the via structures accounts for much of the reliability proble...
Jiwoo Pak, Bei Yu, David Z. Pan
ASPDAC
2015
ACM
20views Hardware» more  ASPDAC 2015»
8 years 7 months ago
Early stage real-time SoC power estimation using RTL instrumentation
Early stage power estimation is critical for SoC architecture exploration and validation in modern VLSI design, but realtime, long time interval and accurate estimation is still c...
Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-F...
ASPDAC
2015
ACM
17views Hardware» more  ASPDAC 2015»
8 years 7 months ago
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power
—Recently, an emerging non-volatile memory called Racetrack Memory (RM) becomes promising to satisfy the requirement of increasing on-chip memory capacity. RM can achieve ultra-h...
Chao Zhang, Guangyu Sun, Weiqi Zhang, Fan Mi, Hai ...