Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay

To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time enabling fast instruction issue logic. Many solutions exist to the scheduling problem, ranging from compile-time to run-time approaches. Compile-time solutions feature fast and simple hardware, but at the expense of conservative schedules. Dynamic schedulers produce high-quality schedules that incorporate run-time information and dependence speculation, but implementing these schedulers requires complex circuits that can slow processor clock speeds. In this paper, we present the Cyclone scheduler, a novel design that captures the benefits of both compileand run-time scheduling. Our approach utilizes a listbased single-pass instruction scheduling algorithm, implemented by hardware at run-time in the front end of the processor pipeline. Once scheduled, instructions are injected into a timed queue that orchestr...

• Type: Conference
• Year: 2003
• Where: ISCA
• Authors: Dan Ernst, Andrew Hamel, Todd M. Austin
• Keywords: Cyclone Scheduler, Hardware, Instruction, ISCA 2003, Run-time