Defect Tolerance at the End of the Roadmap

Defect tolerance will become more important as feature sizes shrink closer to single digit nanometer dimensions. This is true whether the chips are manufactured using topdown methods (e.g., photolithography) or bottom-up methods (e.g., chemically assembled electronic nanotechnology, or CAEN). In this paper, we propose a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. Our methodology is particularly well suited for CAEN.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Mahim Mishra, Seth Copen Goldstein
• Keywords: Defect Tolerance, Defect Tolerance Methodology, Digit Nanometer Dimensions, Hardware, ITC 2003