Desensitization for Power Reduction in Sequential Circuits

In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a portion of the circuit will be deactivated. Consequently, average power consumption in the circuit is reduced at a cost of small increases in area and delay. We present an algorithm for determining the desensitizing signal for each register. A signicant amount of power reduction is achieved in a number of benchmark circuits according to our experimental results.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Xiangfeng Chen, Peichen Pan, C. L. Liu
• Keywords: Average Power Consumption, Computer Architecture, DAC 1996, Power Reduction, Sequential Circuits