Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li...
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more ...
Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O....
-- By taking advantage of the redundancy in a 4-2 compressor, we reduce the number of transitions in carry-save adder trees that are common in large multipliers. Three new 4-2 comp...
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...
Previous work has shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques fo...
Power efficient design of real-time systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper ...
This paper presents a new approach for power reduction by taking a global, software-centric view. It analyzes the sources of power consumption: tasks that require services from ha...