Design and Implementation of a Sort-Free K-Best Sphere Decoder

:- This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as quantized metrics result in a high throughput VLSI architecture with lower power and area consumption compared to state of the art published systems. Functionality is confirmed via an FPGA implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized ASIC implementation in a 65nm CMOS technology.

• Type: Journal
• Year: 2010
• Where: TVLSI
• Authors: Sudip Mondal, Ahmed M. Eltawil, Chung-An Shen, Khaled N. Salama
• Keywords: Artificial Intelligence, Throughput Vlsi Architecture, TVLSI 2010, VLSI Architectural Tradeoffs, Vlsi Architecture