The Design and Performance of a Conflict-Avoiding Cache

High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. In this paper we investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint.

• Type: Conference
• Year: 1997
• Where: MICRO
• Authors: Nigel P. Topham, Antonio González, José González
• Keywords: Cache Conflict-avoidance Schemes, Conflict-avoiding Cache Architectures, Hardware, MICRO 1997, Multi-level Memory Hierarchies