Design of high-performance CMOS charge pumps in phase-locked loops

Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump by the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.

• Type: Conference
• Year: 1999
• Where: ISCAS
• Authors: W. Rhee
• Keywords: Appropriate Charge Pump, Charge Pumps, CMOS Charge Pumps, Hardware, ISCAS 1999