Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation

This paper focuses on numerical function generators (NFGs) based on k-th order polynomial approximations. We show that increasing the polynomial order k reduces significantly the NFG’s memory size. However, larger k requires more logic elements and multipliers. To quantify this tradeoff, we introduce the FPGA utilization measure, and then determine the optimum polynomial order k. Experimental results show that: 1) for low accuracies (up to 17 bits), 1st order polynomial approximations produce the most efficient implementations; and 2) for higher accuracies (18 to 24 bits), 2nd-order polynomial approximations produce the most efficient implementations.

• Type: Conference
• Year: 2007
• Where: DSD
• Authors: Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
• Keywords: DSD 2007, Hardware, K-th Order Polynomial, Order Polynomial Approximations, Polynomial Order