Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model – in posynomial form – is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. Simulation results for design optimization using simultaneous dualVDD and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach.

• Type: Conference
• Year: 2006
• Where: ICCAD
• Authors: Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
• Keywords: Design Optimization, Gate Sizing Techniques, Hardware, ICCAD 2006, Single-event Upsets