VTS
2005
IEEE
14 years 15 days ago
2005
IEEE
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
VTS
2006
IEEE
14 years 28 days ago
2006
IEEE
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
DAC
2006
ACM
14 years 7 months ago
2006
ACM
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...