Detecting resistive shorts for CMOS domino circuits

We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detectable resistance, of intra-gate and inter-gate resistive shorts. We also propose a new keeper design for CMOS domino circuits. The new keeper design has low performance impact and is best useful for small CMOS domino gates. Keepers can eliminate the floating nodes in CMOS domino logic gates.

• Type: Conference
• Year: 1998
• Where: ITC
• Authors: Jonathan T.-Y. Chang, Edward J. McCluskey
• Keywords: CMOS Domino, CMOS Domino Circuits, CMOS Domino Gates, Hardware, ITC 1998