Development cost and size estimation starting from high-level specifications

This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark, the LEON-1 microprocessor, whose VHDL description is of public domain Keywords Project size estimation; design reuse; VHDL; concurrent engineering; Function Point analysis.

• Type: Conference
• Year: 2001
• Where: CODES
• Authors: William Fornaciari, Fabio Salice, Umberto Bondi, Edi Magini
• Keywords: CODES 2001, Size Estimation, Size Estimation Methodology, Software Engineering, VHDL Function Point