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GLVLSI
2006
IEEE

Dominator-based partitioning for delay optimization

14 years 5 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis techniques for delay optimization of large networks. The calculation of dominators is crucial to find topologically ordered clusters suitable for logic restructuring. As a result, a scalable and efficient strategy for delay optimization is proposed and evaluated, showing tangible improvements with respect to existing techniques. A comparison with a standard mincut-based partitioning technique is also presented. Categories and Subject Descriptors: B.6.3 [Hardware]: Logic Design - Design Aids; J.6 [Computer Applications]: Computeraided engineering. Terms: Algorithms, Design.
David Bañeres, Jordi Cortadella, Michael Ki
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where GLVLSI
Authors David Bañeres, Jordi Cortadella, Michael Kishinevsky
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