A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses

Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on-chip buses implemented in Ultra Deep Submicron CMOS technology. Elimination or minimization of crosstalk is crucial to the performance and reliability of SoC designs. This paper presents a novel on-chip bus encoding scheme targeting high performance generic SoC systems. In addition to its efficiency in terms of power, the scheme eliminates three types of crosstalk that cause miller-like transition on two or three adjacent wires simultaneously. The paper describes the technique, its implementation (using the widely adopted AMBA-AHB SoC bus standard) and provides experimental results indicating upto 38% energy saving for systems implemented in 0.18µm CMOS technology.

• Type: Conference
• Year: 2004
• Where: PATMOS
• Authors: Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
• Keywords: CMOS Technology, Crosstalk, Long On-chip Buses, PATMOS 2004