This paper surveys different implementations of dividers on FPGA technology. A special attention is paid on ATP (area-time-power) trade-offs between restoring, non-restoring, and S...
We present SoftExplorer, a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed, and the in...
Eric Senn, Johann Laurent, Nathalie Julien, Eric M...
Motivated by very/ultra large scale integrated circuit (VLSI/ULSI) physical design applications, we study the construction of rectilinear minimum spanning tree (RMST) with its maxi...
Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xia...
This paper investigates the Signal-to-Noise Ratio (SNR) performance of the Logarithmic Number System (LNS) representation against the SNR performance of the fixed-point representa...
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...
Abstract. In this paper we present a new approach to power modeling and runtime power estimation for wireless network interface cards (WNICs). We obtain run-time power estimates by...
Emanuele Lattanzi, Andrea Acquaviva, Alessandro Bo...
Abstract. The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the...
B. Lasbouygues, Robin Wilson, Philippe Maurine, Na...
Synchronization between independently clocked regions in a high performance system is often subject to latencies of more than one clock cycle. We show how the latency can be reduce...
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...