Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies

Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CED techniques, however, require modification in order to be successfully adapted to asynchronous designs. We discuss the limitations of duplication, the simplest CED method, when applied to asynchronous circuits. We demonstrate that such limitations arise mainly due to comparison synchronization issues and inadequate detection of performance-related errors. We propose a circuit that alleviates the difficulties associated with comparison synchronization and we introduce a methodology that enables detection of errors that do not result in logic discrepancies and, thus, may not be detected through comparison. The proposed techniques are illustrated on example circuits, revealing their ability to render concurrently testable asynchronous designs.

• Type: Conference
• Year: 2002
• Where: DFT
• Authors: Thomas Verdel, Yiorgos Makris
• Keywords: Asynchronous Designs, Comparison Synchronization, DFT 2002, Simplest Ced Method, VLSI