DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injection...
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
IDDQ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault-free currents. The concept of current ratios, in which the ratio o...
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
DFT
2002
IEEE
14 years 5 months ago
2002
IEEE
