Dynamic Co-Processor Architecture for Software Acceleration on CSoCs

By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software and hardware execution model. More recently, FPGAs, using new design tools, have also provided support for partial reconfiguration. The system designer is left with the task of interfacing the IP Cores to the CPU and also for realizing partial reconfiguration across the cores. In this paper, we describe a software tool to automate the interface between the CPU and the reconfigurable fabric. Our tool generates hardware wrappers for the IP Cores that makes them look like a C function invocation in the source code. We also use our tool to support partial reconfiguration: the same wrapper is used for a multitude of IP Cores and the user selects the core to be invoked in the program.

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar
• Keywords: Generation Platform Fpgas, Hardware, ICCD 2006, IP Cores, Partial Reconfiguration