Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications

In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applications exhibit high instruction cache miss rates for both the L1 and L2 caches, and a sizable performance improvement can be achieved by eliminating these misses. We show that it is important, not only to address sequential misses, but also misses due to branches and function calls. As a result, we propose an efficient discontinuity prefetching scheme that can be effectively combined with traditional sequential prefetching to address all forms of instruction cache misses. Additionally, with the emergence of chip multiprocessors (CMPs), instruction prefetching schemes must take into account their effect on the shared L2 cache. Specifically, aggressive instruction cache prefetching can result in an increase in the number of L2 cache data misses. As a solution, we propose a scheme that does not install prefetches in...

• Type: Conference
• Year: 2005
• Where: HPCA
• Authors: Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
• Keywords: Cache Data Misses, Computer Architecture, HPCA 2005, Instruction Cache Misses, L2 Cache